1. Field of the Invention
This invention relates generally to digital data processing systems and more specifically, to a method and apparatus for increasing the speed of memory transactions within a computer system.
2. Background Information
As the computer revolution has progressed, the quest of computer hardware developers has been to develop computer systems exhibiting more processing power and faster performance. In order to increase the speed of computer systems, developers place great emphasis in efficiently using the available clock cycles of the central processing unit (processor) to execute the necessary instructions.
A digital data processing system typically consists of a processor and a memory unit. The memory unit stores data in addressable storage locations, and transfers the appropriate data to and from the processor on a data bus upon request by the processor. The processor issues a read request to the memory unit by transmitting an address over the address bus at one clock cycle. The memory unit receives the address, and commences to transmit the corresponding data to the processor on the next clock cycle. FIG. 1A shows a clock diagram for a read transaction.
A write transaction between the processor and the memory unit is carried out differently. The processor issues a write request by transmitting the address and data on the same clock cycle over the address bus and data bus, respectively. FIG. 1B shows a prior art timing diagram for write transactions.
A sequence of mixed reads and writes cannot run at full speed because each type of transaction makes use of the data bus at different times. For example, in order to issue a write request immediately following a read request, the processor must wait until it receives the read data requested from the memory unit. During this process, at least one available clock cycle is wasted, thus decreasing the overall system performance. In order to issue a read request immediately following a write request, the processor must wait until the write transaction is completed at the memory unit. During this process, one available clock cycle is wasted, again slowing the overall system. Therefore, it would be desirable to have a computer system which makes more efficient use of available clock cycles whenever there is a mixture of read and write transactions.